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ltc3226 1 3226fa typical application features description 2-cell supercapacitor charger with backup powerpath controller the ltc ? 3226 is a 2-cell series supercapacitor charger with a backup powerpath controller. it includes a charge pump supercapacitor charger with programmable output voltage, a low dropout regulator, and a power-fail comparator for switching between normal and backup modes. the constant input current supercapacitor charger is designed to charge two supercapacitors in series to a resistor-programmable output voltage of 2.5v to 5.3v. the charger input current limit is programmable by an external resistor at up to 315ma. the internal backup ldo is powered from the superca- pacitors and provides up to 2a peak output current with an adjustable output voltage. when the input supply falls below the power-fail threshold, the ltc3226 automatically enters a backup state in which the supercapacitors power the output through the ldo. the input supply power-fail voltage level is programmed by an external resistor divider. low input noise, low quiescent current and a compact footprint make the ltc3226 ideally suited for small, battery- powered applications. internal current limit and thermal shutdown circuitry allow the device to survive a continu- ous short-circuit from the prog or cpo pins to ground. automatic normal-to-backup mode switchover 3.3v backup supply applications n 1x/2x multimode charge pump supercapacitor charger n automatic cell balancing n ideal diode main powerpath? controller (v in to v out ) n internal 2a ldo backup supply (cpo to v out ) n automatic main/backup switchover n input voltage range: 2.5v to 5.5v n programmable scap charge voltage n programmable input current limit (315ma max) n no load i vin = 55a (typical) n low profile, 16-lead 3mm 3mm qfn package n smart power meters n battery-powered industrial/medical equipment n 3.3v solid-state drives n industrial alarms n data backup supplies n battery hold-up supplies l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 1.2v gate mpext v in v in pfi c + 2.2f 1.96m c C prog en_chg pfo rst capgood gnd charge pump ltc3226 ldo cpo 5v vmid 2.2f v in 3.3v 1.21m c out 47f to load (2a) 33.2k 3.83m c sc 1.2f 255k 80.6k 1.21m 3226 ta01a cpo_fb ldo_fb v out rst_fb + C time (seconds) 0 voltage (v) 3 4 5 1.6 3226 ta01b 2 1 C1 0.4 0.8 1.2 cpo 2.0 0 6 v out v in c sc = 1.2f c out = 47f i load = 2a pfo (2v/div) backup mode (ldo in regulation) backup mode (ldo in dropout)
ltc3226 2 3226fa absolute maximum ratings v in , v out , vmid, cpo, rst , pfo , capgood, ldo_fb ..................................... C0.3v to 6v en_chg, pfi, rst_fb, cpo_fb voltage ............C0.3v to max (v in , cpo) + 0.3v operating junction temperature range (note 3) ...................................................... C40 to 125c storage temperature range ......................C65 to 150c (note 1) order information lead free finish tape and reel part marking* package description temperature range ltc3226eud#pbf ltc3226eud#trpbf lfzv 16-lead (3mm 3mm) plastic qfn C40c to 125c ltc3226iud#pbf ltc3226iud#trpbf lfzv 16-lead (3mm 3mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ pin configuration 16 15 14 13 5 6 7 8 top view 17 gnd ud package 16-lead (3mm w 3mm) plastic qfn 9 10 11 12 4 3 2 1 v out pfo pfi ldo_fb c C capgood cpo_fb prog cpo c + vmid v in gate rst_fb rst en_chg t jmax = 125c, ja = 58.7c/w (note 2) exposed pad (pin 17) is gnd, must be soldered to pcb
ltc3226 3 3226fa electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 3). v in = 3.3v, v cpo = 5v, v out = 3.3v, vmid = 1/2 v cpo unless otherwise noted. symbol parameter conditions min typ max units v in input supply range l 2.5 5.5 v i vin(st) v in quiescent current in normal mode v pfi > 1.2v, v cpo_fb > 1.2v, v in < v cpo 10 a i cpo(st) cpo quiescent current in normal mode v pfi > 1.2v, v cpo_fb > 1.2v, v in < v cpo 20 a i vout(st) v out quiescent current in normal mode v out = v in , v pfi > 1.2v, v cpo_fb > 1.2v, v in < v cpo 5a i cpo(bu) cpo quiescent current in backup mode v pfi < 1.2v, v ldo_fb > 0.8v, v cpo > v out 24 a i vout(bu) v out quiescent current in backup mode v in = 0v, v pfi < 1.2v, v ldo_fb > 0.8v, v cpo > v out 3a ideal diode controller v fwd(eda) external ideal diode forward voltage (v in -v out )i vout = 2ma 15 mv v rto fast turn-off voltage (v in -v out )v in falling C45 mv fast turn-on voltage (v in -v out )v out falling 45 mv charge pump supercapacitor charger v cpo_fb cpo_fb pin threshold for entering sleep mode l 1.18 1.21 1.24 v cpo_fb pin hysteresis for exiting sleep mode 20 mv i cpo_fb charge pump fb pin input leakage v cpo_fb = 1.3v l C50 50 na f osc clk frequency 0.75 0.9 1.05 mhz r ol effective open-loop output impedance (note 4) v cpo = 4.5v, c fly = 1f 6 v prog prog pin servo voltage v cpo_fb < 1.2v l 0.98 1.0 1.02 v i vin(ilim) input current limit r prog = 33.3k, v cpo = 0v 360 ma h prog ratio of v in input current limit to prog pin current r prog = 33.3k, v cpo = 0v 10,500 a/a i chrg(1x) cpo pin charging current (1x mode) v in = 3.8v, r prog = 33.3k, v cpo = 3v 315 ma i chrg(2x) cpo pin charging current (2x mode) r prog = 33.3k 157.5 ma i sc short-circuit charge current prog pin grounded, v cpo = 0v 600 ma v mode v in to cpo voltage differential for switching mode from 1x to 2x 200 mv 1x/2x mode comparator hysteresis 120 mv v clamp maximum voltage across either supercapacitor after charging l 2.65 2.75 v v stack maximum supercapacitor stack voltage l 5.3 5.5 v vmid vmid output voltage 2.5 v vmid current sourcing capability vmid < v cpo /2, v cpo_fb > 1.24v 4.5 ma vmid current sinking capability vmid > v cpo /2, v cpo_fb > 1.24v 5.5 ma cpo_fb pin threshold voltage (rising) for capgood l 1.09 1.11 1.13 v cpo_fb pin hysteresis for capgood 20 mv capgood output low voltage i sink = 5ma 65 mv capgood high impedance leakage current v capgood = 5v l 1a
ltc3226 4 3226fa electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 3). v in = 3.3v, v cpo = 5v, v out = 3.3v, vmid = 1/2 v cpo unless otherwise noted. symbol parameter conditions min typ max units ldo minimum cpo voltage for ldo operation 2.4 v v ldo_fb ldo fb servo voltage i vout = 1ma l 0.76 0.8 0.82 v load regulation v ldo_fb /i out 1ma < i vout < 2a 2.7 mv/a ldo fet r ds(on) v cpo = 3.6v 200 m i ldo_fb(leak) ldo_fb input leakage current v ldo_fb = 0.9v l C60 60 na i lim ldo current limit 24 a rst_fb, rst v rst_fb(th) rst_fb threshold (falling edge) l 0.72 0.74 0.76 v v rst_fb(hys) rst_fb hysteresis 20 mv i rst_fb(leak) rst_fb input leakage current v rst_fb = 0.9v l C50 50 na rst output low voltage i sink = 5ma 65 mv rst high impedance leakage current v rst = 5v l 1a rst delay (rst_fb rising) 290 ms power-fail comparator v pfi(th) pfi input threshold (falling edge) l 1.175 1.2 1.225 v v pfi(hys) pfi input hysteresis 20 mv i pfi(leak) pfi input leakage current v pfi = 0.5v l C50 50 na pfo output low voltage i sink = 5ma 65 mv i pfo(leak ) pfo high impedance leakage current v pfo = 5v l 1a pfi delay to pfo (pfi falling) 0.5 s en_chg v ih input high voltage l 1.3 v v il input low voltage l 0.4 v i ih input high current l C1 1 a i il input low current l C1 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: failure to solder the exposed backside of the package to the pc board ground plane will result in a thermal resistance much greater than 58.7c/w. note 3: the ltc3226 is tested under pulsed load conditions such that t a t j . the ltc3226e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3226i is guaranteed over the full C40c to 125c operating junction temperature range. the junction temperature, t j , is calculated from the ambient temperature, t a , and power dissipation, p d , according to the formula: t j = t a + (p d ? 58.7c/w) note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated thermal package thermal resistance and the environmental factor. note 4: output not in regulation; r ol = (2 ? v in C v cpo )/i cpo .
ltc3226 5 3226fa typical performance characteristics ldo output transient step response waveform charge pump oscillator frequency vs v cpo and temperature charge pump input current vs cpo output voltage charge pump charging current vs cpo output voltage charge pump input current vs v in with cpo grounded ldo load regulation ldo supply regulation ldo regulation voltage vs temperature ldo fet on-resistance vs cpo voltage and temperature cpo voltage (v) 3.6 frequency (khz) 860 880 900 940 4.0 4.4 4.6 3226 g06 840 960 980 920 3.8 4.2 4.8 5.0 v in = 3.3v t = C45c t = 90c t = 25c cpo voltage (v) 0 input current limit (ma) 150 200 250 3 5 3226 g07 100 50 0 12 4 300 350 400 r prog = 33.3k r prog = 100k r prog = 50k 1x mode v in = 3.8v 2x mode cpo voltage (v) 0 cpo charge current (ma) 150 200 250 3 5 3226 g08 100 50 0 12 4 300 350 400 r prog = 33.3k r prog = 100k r prog = 50k 1x mode v in = 3.8v 2x mode v in (v) 3.3 i in (ma) 340 360 3.6 3.9 4.2 4.5 3226 g09 4.8 380 400 330 350 370 390 5.1 90c 25c C45c r prog = 33.2k v cpo = 0v i out (a) 3.280 v out (v) 3.290 3.300 3.275 3.285 3.295 0.001 0.1 1 10 3226 g01 3.270 0.01 cpo = 4v v out set to 3.3v cpo voltage (v) 3.4 3.280 ldo output voltage (v) 3.285 3.295 3.300 3.305 3.6 4.4 4.8 3226 g02 3.290 3.310 4.2 5.2 3.8 4.0 4.6 5.0 i out = 10a v out set to 3.3v temperature (c) C45 v out (v) 3.305 3.315 115 3226 g03 3.295 3.285 C5 35 75 C25 15 55 95 3.325 3.300 3.310 3.290 3.320 v cpo = 5v i out = 1ma cpo voltage (v) 2.2 350 300 250 200 150 100 50 0 3.7 4.7 3226 g04 2.7 3.2 4.2 5.2 r ds(on) (m) t = 90c t = C40c t = 25c load = 500ma v out 50mv/div ac-coupled 1000ma i out 500s/div 3226 g05 500ma t a = 25c, unless otherwise noted.
ltc3226 6 3226fa typical performance characteristics charge profile when top capacitor = bottom capacitor charge profile when top capacitor < bottom capacitor charge profile when top capacitor > bottom capacitor normal-to-back-up mode switching transient waveform leakage balancer source and sink capability vmid shunt regulator voltage vs current and temperature ideal diode gate current vs (v in -v out ) vmid voltage (v) 0 vmid current (ma) 4 8 12 4 3226 g10 0 C4 2 6 10 C2 C6 C8 1 0.5 2 1.5 3 3.5 4.5 2.5 5 vmid sourcing current vmid sinking current 90c 25c C45c v in = 3.3v, v cpo = 5v vmid shunt reg off vmid current (ma) 2.50 vmid voltage (v) 2.60 2.70 2.45 2.55 2.65 0.1 10 100 1000 3226 g11 2.40 1 90c 25c C45c v in = 3.3v v cpo = 5v only leakage balancer active shunt regulator active v in C v out (mv) C100 C5 i gate (a) C4 C2 C1 0 5 2 C50 0 3226 g12 C3 3 4 1 50 100 fast off fast on linear region forward voltage voltage (v) 3226 g13 time (5 seconds/div) cpo v in v mid 1x mode 2x mode r prog = 33.2k c sc = 1.2f 6 5 4 3 2 1 C1 0 voltage (v) 3226 g14 time (5 seconds/div) 6 5 4 3 2 1 0 C1 v in v mid 1x mode 2x mode r prog = 33.2k, c sc = 1.2f extra 1.5f between cpo and v mid cpo v mid clamped (shunt active) voltage (v) 3226 g16 0 100 200 300 400 500 time (s) 4 3 2 1 0 v in v out pfo (1v/div) c sc = 1.2f c out = 47f i load = 2a t a = 25c, unless otherwise noted. voltage (v) 3226 g15 time (5 seconds/div) 6 5 4 3 2 1 0 C1 v in v mid 1x mode 2x mode r prog = 33.2k, c sc = 1.2f, extra 1.5f between v mid and gnd cpo top cap clamped
ltc3226 7 3226fa pin functions v out (pin 1): voltage output. this pin is used to provide power to an external load from either the primary input supply (v in ) or the supercapacitor (cpo) if the primary input supply is not available. v out should be bypassed with a low esr ceramic capacitor of at least 47f capaci- tance to gnd. pfo (pin 2): open-drain power-fail status output. this pin is pulled to ground by an internal n-channel mosfet when the pfi input is below 1.2v. once the pfi input re- covers, this pin becomes high impedance. pfi (pin 3): power-fail input. high impedance input to an accurate comparator with a 1.2v falling threshold and 20mv hysteresis. this pin controls the state of the pfo output pin and the operating mode of the ltc3226. ldo_fb (pin 4): internal ldo feedback pin. the voltage on this pin is compared to the internal reference voltage (0.8v) by the error amplifier to keep the output in regula- tion. an external resistor divider is required between v out , ldo_fb and gnd to program the ldo output voltage. see the applications information section. gate (pin 5): external fet gate pin. this pin is driven by an internal ideal diode controller to regulate v out to 15mv below v in . rst_fb (pin 6): reset comparator input. high imped- ance input to an accurate comparator with a 0.74v falling threshold and 20mv hysteresis. this pin controls the state of the rst output pin. an external resistor divider is required between v out , rst_fb and gnd. it can be the same resistor divider as the ldo_fb divider. see the applications information section. rst (pin 7): open-drain status output of the reset comparator. this pin is pulled to ground by an internal n-channel mosfet whenever the rst_fb pin voltage falls below 0.74v. once the rst_fb pin voltage recovers, the pin becomes high impedance after a 290ms delay indicat- ing that v out is within 7.5% of its programmed value. en_chg (pin 8): enable pin for the charge pump super- capacitor charger with an internal pull-up. tie this pin to a voltage below 0.4v to disable the internal charge pump. prog (pin 9): charger input current limit programming pin. a resistor connected between this pin and gnd sets the input current limit for the charger. see the applications information section. cpo_fb (pin 10): feedback pin for the charge pump. the voltage on this pin is compared to the internal reference voltage (1.2v) to keep the charge pump output cpo in regulation. an external resistor divider is required between cpo, cpo_fb and gnd to program the cpo output volt- age. see the applications information section. capgood (pin 11): open-drain status output of the cpo voltage. this pin is pulled to ground by an internal n-channel mosfet until cpo_fb pin reaches 1.11v. once the cpo_fb pin exceeds 1.11v, this pin becomes high impedance indicating that the cpo voltage is within 7.5% of its target value. c C (pin 12): internal charge pump flying capacitor negative terminal. v in (pin 13): primary input supply. this pin supplies power to the v out pin through an external p-channel mosfet and also to the supercapacitors attached to the cpo and vmid pins. v in should be bypassed to gnd with a low esr ceramic capacitor of at least 2.2f depending on the load transient. vmid (pin 14): midpoint of two series supercapacitors. c + (pin 15): internal charge pump flying capacitor positive terminal. a 1f to 10f x5r or x7r ceramic capacitor should be connected from c + to c C . cpo (pin 16): backup supply pin. connect cpo to the top plate of the top supercapacitor. this pin receives power from v in through an internal charge pump doubler and supplies power to v out through an internal ldo when the primary input supply has failed. gnd (exposed pad pin 17): ground. the exposed pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the part to achieve optimal thermal performance.
ltc3226 8 3226fa block diagram + C 7 6 4 5 3 + C 0.8v 0.74v ldo_fb rst_fb 16 cpo 14 vmid 10 cpo_fb capgood rst ldo gate external pfet 1.2v pfi v in 2.5v to 5.5v r pf1 r fb1 c out v out r fb2 r cp2 3226 f01 r cp1 r pf2 8 en_chg 9 prog r prog 15 c + 17 gnd 12 c C 2.2f 13 v in 2 pfo 15mv ideal diode controller 1.11v C + C + 1v C + delay + C 1x/2x mode charge pump 2.65v clamp/ balancer 11 c sc C + figure 1. ltc3226 block diagram
ltc3226 9 3226fa operation the ltc3226 is a 2-cell series supercapacitor charger designed to back up a li-ion battery or any system rail in the range of 2.5v to 5.3v. it has four principal circuit components: a dual mode (1x/2x) charge pump with an integrated balancer and a voltage clamp, an ldo to supply the load current from the charge stored on the superca- pacitor, an ideal diode controller to control the gate of the external fet between v in and v out , and a pfi comparator to decide whether to activate the charge pump to charge the supercapacitor stack or to activate the ldo to supply the load when v in falls below an externally programmed value. the ltc3226 has two modes of operation: normal and backup. if v in is above an externally programmable pfi threshold voltage, the part is in normal mode in which power flows from v in to v out through the external fet and the internal charge pump stays on to top off the supercapacitor stack. if v in is below this pfi threshold, the part is in backup mode. in this mode, the internal charge pump is turned off, the external fet is turned off and the ldo is turned on to supply the load current from the stored charge. charge pump one of the principal circuit components of the ltc3226 is a dual mode low noise constant frequency (0.9mhz) regulated charge pump which transfers charge from v in and stores it onto the supercapacitor stack at the cpo pin. the target or termination voltage on the cpo pin is pro- grammed by an external resistor divider using the cpo_fb pin. the input current limit to the charger is programmed by an external resistor between the prog pin and ground. the charge pump turns on when v in exceeds the externally programmable pfi threshold. at the beginning of the charge cycle when the cpo pin voltage is less than v in , the charge pump is in 1x mode (linear mode) in which the charge pump acts as a pass element and charges the supercapacitor with a charge current that is limited by the programmed input current limit. as the cpo voltage rises to within 200mv of the input supply voltage, the charge pump switches to 2x mode (doubler mode) in which the average charge current is approximately equal to half the input current limit. as the cpo voltage exceeds the target value by approximately 1%, the charge pump switches turn off and the charge pump enters the sleep mode. in sleep mode, most of the charge pump control circuitry is turned off to minimize quiescent current. as the supercapacitor discharges due to leakage and internal quiescent current load, the cpo pin voltage slowly drops. when the cpo pin voltage drops 1% below the programmed voltage, the charge pump turns on to replenish charge on the supercapacitor and the cycle con- tinues. the charge pump can be turned off by pulling the en_chg pin below 0.4v. however, by default, the charge pump is always enabled via an internal low current pull-up circuit if the en_chg pin is left floating. voltage clamp the ltc3226 charge pump is equipped with circuitry to limit the voltage across any supercapacitor in the stack to a maximum allowable preset voltage of 2.65v. if the voltage across the top capacitor (vmid-v cpo ) ever gets to 2.65v before the cpo pin reaches the target voltage, the charge pump stops charging the top of the stack via the cpo pin, switches to 1x mode and delivers charge directly to the bottom capacitor via the vmid pin until the stack voltage reaches its programmed value. if the voltage across the bottom capacitor reaches 2.65v before the stack gets to its target value, the charge pump continues to deliver charge to the top of the stack via the cpo pin and a shunt regulator turns on to bleed charge off of the bottom capacitor and prevents the vmid pin voltage from rising any further. the shunt regulator is able to shunt the maximum allowable charge current which is approximately 315ma (in 1x mode). in the event both capacitors exceed 2.65v, the charge pump enters sleep mode by turning off most of its circuitry. leakage balancer the ltc3226 is equipped with an internal leakage balanc- ing amplifier which servos the vmid pin voltage to exactly half of the cpo pin voltage. however, it has limited source (~4.5ma) and sink (~5.5ma) capability. it is designed to handle slight mismatch of the supercapacitors due to leakage currents; not to correct any gross mismatch due to defects. the balancer is only active as long as the input supply voltage is above the pfi threshold. the internal bal- ancer eliminates the need for external balancing resistors.
ltc3226 10 3226fa operation capgood status output the ltc3226 charge pump includes a comparator to re- port the status of the supercapacitors via an open-drain nmos transistor on the capgood pin. this pin is pulled to ground until the cpo pin voltage rises to within 7.5% of the programmed value. once the cpo pin is above this threshold, the capgood pin goes high impedance. prog pin short-circuit protection typically the maximum current that the ltc3226 charge pump can deliver is set by the prog resistor. however, if for any reason, the prog pin gets shorted to gnd, or the user chooses a prog resistor value which is far smaller than recommended, the charge pump input current is limited to an internally set value of approximately 600ma. also the maximum current that can be sourced from the prog pin is limited by an internal resistor to less than 1ma. low dropout regulator (ldo) another principal circuit component of the ltc3226 is the low dropout regulator (ldo) which transfers power from the supercapacitor stack to v out through a pass element with an r ds(on) of approximately 200m. this ldo has a current limit internally set to 4a. in the event that the input supply voltage falls below the pfi threshold, the pfi comparator promptly turns on the ldo to supply the nec- essary load without letting the v out rail droop too much. however, to prevent unrestricted current flow from the input to the supercapacitors through the ideal diode, the ldo is turned off until the cpo voltage is greater than v in by 100mv typical. the ldo output voltage is programmed through an external resistor divider via the ldo_fb pin. power-fail (pfi) comparator the ltc3226 contains a fast comparator which switches the part from normal to backup mode in the event the input voltage, v in , falls below an externally programmed threshold voltage. in backup mode, the charge pump shuts off and the ldo powers the load as long as there is enough charge stored on the supercapacitors. the pfi threshold voltage is programmed by an external resistor divider via the pfi pin. the output of the pfi comparator also drives the gate of an open-drain nmos to report the status via the pfo pin. in normal mode, the pfo pin is high impedance but in backup mode, the pin is pulled down to ground. ideal diode controller the ltc3226 contains an ideal diode controller which controls the gate of an external pfet connected between the input, v in , and the output, v out , through the gate pin. under normal operating conditions, this external fet constitutes the main power path from input to output. for very light loads, the controller maintains a 15mv delta across the fet between the input and output voltage. in the event v in suddenly drops below v out , the controller quickly turns the fet completely off to prevent any reverse conduction from v out back to the input supply. reset comparator the ltc3226 contains a reset comparator which moni- tors v out under all operating modes via the rst_fb pin and reports the status via an open-drain nmos transis- tor on the rst pin. at any time, if v out falls 7.5% from its programmed value, it pulls the rst pin low almost instantaneously. however, on the rising edge the compara- tor waits 290ms after v out crosses the threshold before making the rst pin high impedance. global thermal shutdown the ltc3226 includes a global thermal shutdown which shuts down the entire part in the event the die temperature exceeds 152c. it resumes normal operation once the temperature drops by about 15c to approximately 137c.
ltc3226 11 3226fa applications information programming the supercapacitor termination voltage (cpo) the termination voltage of the supercapacitor stack on the cpo pin can be programmed for any voltage between 2.5v to 5.3v by using a resistor divider from the cpo pin to gnd via the cpo_fb pin such that: v cpo = v cpo _fb ?1 + r cp1 r cp2 ? ? ? ? ? ? where v cpo_fb is 1.2v. see the block diagram in figure?1. typical values for r cp1 and r cp2 are in the range of 40k to 5m. programming the input current limit for the charger the input current limit for the ltc3226 charge pump is programmed by using a single resistor from the prog pin to ground. the input current limit is typically 10,500 times the current out of the prog pin. the prog pin voltage always servos to 1v as long as the part is not in sleep mode. the program resistor and the input current limit are calculated using the following equations: r prog = 10,500 ? 1v i vin(ilim) , i vin(ilim) = 10,500 ? 1v r prog where i vin(ilim) is the input current limit for the charge pump charger. the maximum allowable input current limit of 315ma can be achieved by using a prog resistor of 33.2k. to maximize the charge transfer rate, the charge pump operates in 1x mode when the supercapacitor voltage is less than the input voltage and the charge current out of cpo pin is only limited by the programmed input current limit. however, in 2x mode, the average charge current is approximately half the input current limit. programming the input voltage threshold for the power-fail comparator the input voltage threshold below which the power-fail status pin pfo indicates a power-fail condition and the ltc3226 switches the internal ldo on can be programmed by using a resistor divider from the v in pin to gnd via the pfi pin such that: v in(pfo _ hi _ lo) = v pfi ?1 + r pf1 r pf2 ? ? ? ? ? ? where v pfi is 1.2v. see figure 1. typical values for r pf1 and r pf2 are in the range of 40k to 5m. for a smooth transition from normal to back-up mode, the pfi threshold should be set 50mv to 100mv above the programmed ldo output voltage, v out . the input voltage above which the power-fail status pin pfo is high impedance and the supercapacitor charger and the ideal diode are enabled is: v in(pfo _ lo _ hi) = v pfi + v pfi(hys) () ?1 + r pf1 r pf2 ? ? ? ? ? ? where v pfi(hys) is the hysteresis of the pfi comparator. it is internally set to a typical value of 20mv. the hysteresis can be increased externally by adding a resistor, r h , in series with a diode, d1, between the pfo and pfi pins as shown in figure 2. this network will increase the low-to-high v in threshold for pfo while keeping the high-to-low threshold intact. the increase in hysteresis at the input can be calculated as shown: v in(hys) = v pfi + v pfi(hys) ?v f () ? r pf1 r h
ltc3226 12 3226fa applications information where v f is the forward voltage of the diode. as an ex- ample, if r pf1 = 200k, r pf2 = 120k, r h = 2m, and v f = 0.4v, the additional hysteresis provided by this network can be calculated using the above equation as follows: v in(hys) = 1.2 + 0.02 ? 0.4 () v? 200k 2m = 82mv gnd is needed to set v out and the reset threshold 7.5% below the v out programmed voltage. however, the reset threshold can be set independent of v out by an additional resistor divider. effective open-loop output resistance (r ol ) of the charge pump the effective open-loop output resistance (r ol ) of a charge pump determines the strength of a charge pump. the value of this parameter depends on many factors such as the oscillator frequency (f osc ), value of the flying capacitor (c fly ), the nonoverlap time, the internal switch resistances (r s ), and the esr of the external capacitors. a first order approximation of r ol is given below: r ol ? 2 s = 1to 4 r s + 1 f osc ?c fly for the ltc3226 charge pump, the sum of the switch resistances is approximately 2.5 in a typical applica- tion where v in = 3.3v and v cpo = 5v. for c fly = 1f and f osc = 1mhz, the effective open-loop output resistance of the charge pump can be approximated from the above equation as follows: r ol ? 2 ? 2.5 + 1 1m h z ? 1 f = 6 maximum available charge current in the absence of any internal current limit, the maximum available current out of a charge pump in 2x mode can be calculated from the charge pump input and output voltage and the effective open-loop output resistance r ol using the following equation: i chrg = 2v in ?v cpo r ol for example, if the ltc3226 charge pump (r ol ? 6) has to charge a supercapacitor to 5v from 2.5v input, the charge current available when v cpo = 4.8v can be calculated as follows: i chrg = 2 ? 2.5v ? 4.8v 6 = 33.3ma 3226 f02 ltc3226 d1 v in v out pfo pfi 470k r pf1 r h r pf2 figure 2. increasing pfi comparator hysteresis externally programming the ldo output voltage (v out ) the ldo output voltage in backup mode can be pro- grammed for any voltage between 2.5v to 5.3v by using a resistor divider from the v out pin to gnd via the ldo_fb pin such that: v out = v ldo _fb ?1 + r fb1 r fb2 ? ? ? ? ? ? where v ldo_fb is 0.8v. see the block diagram in figure 1. typical values for r fb1 and r fb2 are in the range of 40k to 500k. too small a resistor will result in a large quiescent current whereas too large a resistor coupled with ldo_fb pin capacitance will create an additional pole and may cause loop instability. programming the reset threshold the threshold for the reset comparator can be programmed by using a resistor divider from the v out pin to gnd via the rst_fb pin such that: v out = v rst _ fb ?1 + r fb1 r fb2 ? ? ? ? ? ? where v rst_fb is 0.74v. see figure 1. typical values for r fb1 and r fb3 are in the range of 40k to 5m. in most ap- plications, the ldo_fb and rst_fb pins can be shorted together and only one resistor divider between v out and
ltc3226 13 3226fa applications information so even if the charge pump input current limit is pro- grammed for 315ma (r prog = 33.2k), the actual charge current will be considerably less than 157.5ma (half of programmed limit) in 2x mode for very low input supply. for v in = 2.5v, the cpo voltage above which the charge current will decrease from the programmed value of 157.5ma (r prog = 33.2k) can be calculated from the previous equation as follows: v cpo = (2 ? 2.5v C 157.5ma ? 6) = 4.055v choosing the ldo output capacitor in the event v in falls below the programmed pfi threshold, the pfi comparator turns off the charge pump and turns on the internal ldo to supply the load from the backed- up supercapacitor storage. however, due to the delay associated with the pfi comparator and ldo circuitry, it could be up to 2s before the ldo is capable of supplying the load demand at v out . in order to prevent v out from drooping too much during this transition, a 47f ceramic capacitor is recommended at the v out terminal. for any output capacitance, c out , delay, t, and load current, i load , the drop in v out , ? v, can be calculated using the following equation: i load = c out ? v t for example, if v out can not tolerate more than 100mv drop under a maximum load of 2a during this transition, the minimum capacitance required at the ldo output can be calculated using the above equation as follows: c out(min) = 2a ? 2s 100mv = 40f charging a single supercapacitor the ltc3226 can also be used to charge a single super- capacitor by connecting two series-connected matched ceramic capacitors with a minimum capacitance of 100f in parallel with the supercapacitor as shown in figure 3. supercapacitor manufacturers refer to the following table for supercapacitor manu- facturers. table 1. supercapacitor manufacturers cap-xx www.cap-xx.com ness cap www.nesscap.com maxwell www.maxwell.com bussmann www.cooperbussmann.com avx www.avx.com illinois capacitor www.illinoiscapacitor.com tecate group www.tecategroup.com board layout considerations due to high switching frequency and high transient cur- rents produced by the ltc3226 charge pump, careful board layout is necessary for optimum performance. a true ground plane and short connections to all of the external capacitors will improve performance. also, to be able to deliver maximum load current from the ldo under all conditions, it is critical that the exposed metal pad on the backside of the qfn package has a good thermal contact to the pc board ground plane. lack of proper thermal contact can cause the junction temperature to exceed the threshold for thermal shutdown. figure 3. charging a single supercapacitor c1 c2 c sup 3226 f03 cpo ltc3226 vmid gnd
ltc3226 14 3226fa ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 p 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 p 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 bottom viewexposed pad 1.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 1 pin 1 notch r = 0.20 typ or 0.25 s 45 o chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 p 0.05 3.50 p 0.05 0.70 p 0.05 0.00 C 0.05 (ud16) qfn 0904 0.25 p 0.05 0.50 bsc package outline package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3226 15 3226fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 5/12 added note 3 to operating junction temperature range modified basic default conditions for electrical characteristics modified test conditions for note 3 2 3, 4 4
ltc3226 16 3226fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0512 rev a ? printed in usa related parts typical application li-ion backup supply v out gate mpext v in pfi c + c fly 2.2f r1 2.21m r2 1.21m c C prog en_chg h/l rst pfo capgood gnd ltc3226 cpo vmid c1 4.7f li-ion 47f to load 5v r prog 33.2k r4 3.83m c sc 1.2f r6 1.21m r3 255k r4 80.6k 470k c sc : cap-xx hs230 mpext: vishay si2333 470k 470k 3226 ta02 cpo_fb ldo_fb rst_fb + p part number description comments ltc3225/ ltc3225-1 150ma supercapacitor charger low noise, constant frequency charging of two series supercapacitors. automatic cell balancing prevents capacitor overvoltage during charging. programmable charge current (up to 150ma). selectable 2.4v or 2.65v regulation per cell (ltc3225), selectable 2v or 2.25v regulation per cell (ltc3225-1). 2mm 3mm dfn package lt3485 photoflash capacitor chargers with output voltage monitor and integrated igbt drive integrated igbt driver; voltage output monitor; uses small transformers: 5.8mm 5.8mm 3mm. operates from two aa batteries, single cell li-ion or any supply from 1.8v up to 10v. no output voltage divider needed; no external schottky diode required. charges any size photoflash capacitor; 10-lead (3mm 3mm) dfn package ltc3625/ ltc3625-1 1a high efficiency 2-cell supercapacitor charger with automatic cell balancing high efficiency step-up/step-down charging of two series supercapacitors. automatic cell balancing prevents capacitor overvoltage during charging. programmable charging current up to 500ma (single inductor), 1a (dual inductor). v in = 2.7v to 5.5v, selectable 2.4v/2.65v regulation per cell (ltc3625). selectable 2v/2.25v regulation per cell (ltc3625-1), low no-load quiescent current: 23a. 12-lead 3mm 4mm dfn package lt3750 capacitor charger controller charges any size capacitor; easily adjustable output voltage. drives high current nmos fets; primary-side senseno output voltage divider necessary. wide input range: 3v to 24v; drives gate to v cc C 2v. 10-lead ms package lt3751 high voltage capacitor charger controller with regulation charges any size capacitor; low noise output in voltage regulation mode. stable operation under a no-load condition; integrated 2a mosfet gate driver with rail-to-rail operation for v cc 8v. selectable 5.6v or 10.5v internal gate drive voltage clamp; user-selectable over/undervoltage detect. easily adjustable output voltage; primary or secondary side output voltage sense. wide input v cc voltage range (5v to 24v). 20-pin qfn 4mm 5mm and 20-lead tssop packages LTC4425 supercapacitor charger with current limited ideal diode constant-current/constant-voltage linear charger for 2-cell series supercapacitor stack. v in : li-ion/polymer battery, a usb port, or a 2.7v to 5.5v current-limited supply. 2a charge current, auto cell balancing, 20a quiescent current, shutdown current <2a. low profile 12-pin 3mm 3mm dfn or a 12-lead msop package

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